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Master's Dissertation
DOI
https://doi.org/10.11606/D.55.2022.tde-27072022-085504
Document
Author
Full name
Caio César Soares Oliveira
E-mail
Institute/School/College
Knowledge Area
Date of Defense
Published
São Carlos, 2022
Supervisor
Committee
Bonato, Vanderlei (President)
Araújo, Guido Costa Souza de
Delbem, Alexandre Cláudio Botazzo
Matias, Paulo
Title in English
A FAST Hardware Decoder Optimized for Template Features to Obtain Order Book Data in Low Latency
Keywords in English
FIX/FAST Decoder
FPGA
HFT
Abstract in English
High-Frequency Trading (HFT) systems require high computational performance for real-time trading and data analysis. The FAST protocol, an extension of the FIX protocol, is one of the main patterns adopted by these systems. This work implements an open-source component in FPGA-based hardware to decode financial messages and output the necessary tags for order book updates. The component implements the FAST and FIX protocols versions adopted by the B3 Brazilian stock exchange. The proposed hardware decodes messages with an average latency of 0.72us, and average throughput of 1.4 millions FAST messages per second, representing a reduction of two orders of magnitude compared to the same implementation executed in a software processo.
Title in Portuguese
Um Decodificador FAST em Hardware Otimizado de Acordo com o Template para Obter Dados do Livro de Ofertas em Baixa Latência
Keywords in Portuguese
Decodificador FIX/FAST
FPGA
HFT
Abstract in Portuguese
Os sistemas do tipo High Frequency Trading (HFT) exigem alto desempenho computacional para negociação em tempo real e para análise de dados. O protocolo FAST, uma extensão do protocolo FIX, é um dos principais padrões adotado por esses sistemas. Este trabalho implementa um componente open source em hardware baseado em FPGA para decodificar mensagens financeiras e emitir as tags necessárias para atualização do livro de ofertas. O componente implementa as versões dos protocolos FAST e FIX adotados pela bolsa brasileira B3. O hardware proposto decodifica mensagens com latência média de 0.72us, e throughput médio de 1.4 milhões de mensagens FAST por segundo, representando uma redução de duas ordens de magnitude em comparação com a mesma implementação executada em processador de software.
 
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Publishing Date
2022-07-27
 
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