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Master's Dissertation
DOI
10.11606/D.55.2005.tde-31082005-120141
Document
Author
Full name
Ricardo Menotti
E-mail
Institute/School/College
Knowledge Area
Date of Defense
Published
São Carlos, 2005
Supervisor
Committee
Marques, Eduardo (President)
Fernandes, Marcio Merino
Silva, Jorge Luiz e
Title in Portuguese
Implementação de um módulo Ethernet 10/100Mbps com interface Avalon para o processador Nios II da Altera
Keywords in Portuguese
Computação Reconfigurável
Ethernet
FPGA
Sistemas Embutidos
SoC
SoPC
Abstract in Portuguese
O presente trabalho apresenta a implementação de um core de rede Ethernet 10/100Mbps com interface para o barramento Avalon para utilização em conjunto com o processador Nios II da Altera. A tecnologia Ethernet foi implementada em computação reconfigurável e utilizou-se como base um módulo disponível na Internet denominado OpenCores MAC 10/100. O projeto foi desenvolvido para ser aplicado em sistemas embarcados, mais especificamente para o uso em um robô móvel em desenvolvimento no Laboratório de Computação Reconfigurável do ICMC/USP. O core foi incorporado à biblioteca da ferramenta SoPC Builder da Altera, visando uma fácil integração do mesmo em outros projetos. Foram utilizadas as ferramentas Quartus II e ModelSim para o desenvolvimento e testes do sistema, além de dois kits Nios versão Stratix para a validação do projeto, sendo as placas interligadas ponto-a-ponto sem a utilizaçao de transceivers analógicos.
Title in English
Implementation of an Ethernet 10/100Mbps core with Avalon interface for Nios II processor from Altera
Keywords in English
Embedded Systems
Ethernet
FPGA
Reconfigurable Computing
SoC
SoPC
Abstract in English
This work presents the implementation of a network Ethernet 10/100Mbps core with interfaces to Avalon bus for using with the Nios II processor from Altera. The Ethernet technology was implemented in reconfigurable computing and was based in the OpenCores MAC 10/100 available on Internet. The project was developed for embedded systems applications, more specifically for a mobile robot in development at Reconfigurable Computing Laboratory from ICMC/USP. The core was incorporated to SoPC Builder tool’s library from Altera, aiming to facilitate the integration with others projects. To development and system tests were used Quartus II and ModelSim, and two Nios Development kit Statix Edition for project validation. The boards were linked peer-to-peer, without use analog transceivers.
 
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disserta.pdf (4.46 Mbytes)
Publishing Date
2005-11-11
 
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