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Master's Dissertation
DOI
https://doi.org/10.11606/D.55.2009.tde-05032010-203142
Document
Author
Full name
Vitor Fiorotto Astolfi
Institute/School/College
Knowledge Area
Date of Defense
Published
São Carlos, 2009
Supervisor
Committee
Silva, Jorge Luiz e (President)
Bonato, Vanderlei
Fernandes, Marcio Merino
Title in Portuguese
ChipCflow - em hardware dinamicamente reconfigurável
Keywords in Portuguese
Arquitetura a fluxo de dados
Computação reconfigurável
FPGA
Reconfiguração parcial dinâmica
Virtex
Abstract in Portuguese
Nos últimos anos, houve um grande avanço na computação reconfigurável, em particular em hardware que emprega Field-Programmable Gate Arrays. Porém, esse aumento de capacidade e desempenho aumentou a distância entre a capacidade de projeto e a disponibilidade de tecnologia para o desenvolvimento do projeto. As linguagens de programação imperativas de alto nível, como C, são mais apropriadas para o desenvolvimento de aplicativos complexos que as linguagens de descrição de hardware. Por isso, surgiram diversas ferramentas para o desenvolvimento de hardware a partir de código em C. A ferramenta ChipCflow, da qual faz parte este projeto, é uma delas. A execução dos programas por meio dessa ferramenta será completamente baseada em seu fluxo de dados, seguindo o modelo dinâmico encontrado nas arquiteturas de computadores a fluxo de dados, aproveitando ao máximo o paralelismo considerado natural desse modelo e as características do hardware parcialmente reconfigurável. Neste projeto em particular, o objetivo é a prova de conceito (proof of concept) para a criação de instâncias, em forma de operadores, de um algoritmo ChipCflow em hardware parcialmente reconfigurável, tendo como base a plataforma Virtex da Xilinx
Title in English
ChipCflow - in dynamically reconfigurable hardware
Keywords in English
Dataflow architecture
Dynamic partial reconfiguration
FPGA
Reconfigurable computing
Virtex
Abstract in English
In recent years, reconfigurable computing has become increasingly more advanced, especially in hardware that uses Field-Programmable Gate Arrays. However, the increase of performance in FPGAs accumulated the gap between design capacity and technology for the development of the design. Imperative high-level programming languages such as C are more appropriate for the development of complex algorithms than hardware description languages (HDL). For this reason, many ANSI C-like programming tools for the development of hardware came to existence. The ChipCflow project, of which this project is part, is one of these tools. The execution of algorithms through this tool will be completely directed by data flow, according to the dynamic model found on Dataflow Architectures, taking advantage of its natural high levels of parallelism and the characteristics of the partially reconfigurable hardware. In this project, the objective is a proof of concept for the creation of instances, in the form of operators, of a ChipCflow algorithm on a partially reconfigurable hardware, taking as reference the Xilinx Virtex boards
 
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Publishing Date
2010-06-08
 
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