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Doctoral Thesis
DOI
https://doi.org/10.11606/T.3.2017.tde-05102017-082520
Document
Author
Full name
Claudio Garcia
E-mail
Institute/School/College
Knowledge Area
Date of Defense
Published
São Paulo, 1992
Supervisor
Committee
Martucci Junior, Moacyr (President)
Catto, Artur Joao
Melnikoff, Selma Shin Shimizu
Panetta, Jairo
Zuffo, Joao Antonio
Title in Portuguese
Escalação estática de tarefas parcialmente ordenadas em redes de Transputers.
Keywords in Portuguese
Algoritmos
Distribuição de tarefas em processadores
Escalação estática
Heurística
Processamento paralelo
Redes de Transputers
Abstract in Portuguese
Em certas aplicações, a redução no tempo de processamento de programas é fundamental. Em sistemas multiprocessados, busca-se minimizar esse tempo através de algoritmos que proveem escalamento estático das tarefas nos processadores. Esses algoritmos podem ser exatos, significando que o tempo de processamento resultante é o mínimo para uma dada arquitetura de hardware, ou aproximados, indicando que a solução obtida e sub-ótima. Este trabalho apresenta uma biblioteca de algoritmos heurísticos que fornecem escalamentos sub-ótimos e um modelo que simula a operação de redes de transputers. Cada escalamento gerado é testado na rede simulada e seu tempo de processamento é avaliado. Após ter verificado o desempenho de todos os algoritmos disponíveis, é apresentado como resposta o melhor escalamento testado e seu tempo simulado de processamento. O usuário pode então alocar as tarefas nos transputers, de acordo com a ordem e o regime de operação (seq ou par) fornecidos. O programa escalador foi testado com diversos arranjos de tarefas parcialmente ordenadas em diferentes arquiteturas de transputers, para verificar a conformidade do modelo da rede de processadores com a realidade. Os resultados dos testes atenderam plenamente aos requisitos de desempenho, apresentando desvios máximos em torno de 1%.
Title in English
Suboptimal static scaling of partially ordered tasks in Transputer networks.
Keywords in English
Distribution of tasks in processors
Parallel processing
Static scheduling
Transputer networks
Abstract in English
In certain scientific applications the reduction in the processing time is fundamental. In the processing area and, particularly, in multiprocessing, the minimization of this time through algorithms that provide static scheduling of tasks in processors is aimed. These algorithms can be exact, meaning that the resulting processing time is minimum for a certain hardware architecture or approximate, indicating that the solution obtained is sub-optimal. This work presents a library of heuristic algorithms that provide sub-optimal scheduling and a model that simulates the operation of any Transputers network. Together they constitute the computational tool here nominated Scheduling Program. Each schedule created is tested in the simulated network and its processing time is evaluated. After verifying the performance of every available heuristic algorithms, the Scheduling Program provides as response the best tested schedule and its simulated processing time. Then the user can allocate the tasks on the Transputers, following the order and the construction (SEQ or PAR) provided. The Scheduling Program was tested on several partially ordered tasks arrangements in different Transputers architectures to check the conformity of the processors networks model with reality. The results of the tests complied completely to the performance requirements, presenting a maximum deviation of about 1%.
 
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ClaudioGarcia_T.pdf (14.60 Mbytes)
Publishing Date
2017-10-05
 
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